1. Field of the Invention
The present invention relates to an optical transmission apparatus.
2. Description of the Related Art
In a redundant network configured according to a standard of optical transmission technology such as Synchronous Digital Hierarchy (SDH) or Synchronous Optical Network (SONET), a working line and a protection line are provided between two optical transmission apparatuses. Further, an Automatic Protection Switch (APS) function is provided for switching the working line to the protection line upon the occurrence of failure on the working line, so as to quickly respond to communication failure.
An example of such network configuration implementing the APS function is a network configuration called “1+1 APS” shown in FIGS. 9A to 9D. FIGS. 9A to 9D are schematic drawings for explaining the 1+1 APS.
In the “1+1 APS” as shown in FIGS. 9A to 9D, redundant lines are provided as a working line and a protection line between two optical transmission apparatuses. In the normal operation shown in FIG. 9A, an optical signal from an optical transmission apparatus on the left is forwarded to an optical transmission apparatus on the right over both the working line and the protection line, and a selector (see “SEL” of FIG. 9A) of the right optical transmission apparatus at the receiving end controls switching so as to receive the optical signal only from the working line. An optical signal from the right optical transmission apparatus is forwarded to the left optical transmission apparatus over both the working line and the protection line, and a selector of the left optical transmission apparatus at the receiving end controls switching so as to receive the optical signal only from the working line.
In the “1+1 APS”, upon occurrence of communication failure on the working line, a selector of an optical transmission apparatus controls switching so as to receive an optical signal from a neighboring optical transmission apparatus over the protection line. Specifically, as shown in FIG. 9B, switching is performed at the receiving end so that an optical signal sent over the protection line is received as well. In this way, communication failure can be quickly responded only by performing switching control at the receiving end.
After recovery from the communication failure, normal operation may be performed using the protection line as a working line and the recovered working line as a protection line as shown in FIG. 9C, or switching may be performed back again as shown in FIG. 9D.
A network configuration so-called “1:1 APS” has also been known that performs switching control at both the receiving end and the sending end of an optical signal.
Another example of the network configuration implementing the APS function is a ring network as shown in FIGS. 10A and 10B, so-called “Bidirectional Line Switch Ring (BLSR)” that performs switching control of the “1+1 APS”. FIGS. 10A and 10B are schematic drawings for explaining the BLSR.
In the normal operation of the “BLSR”, an optical signal is communicated using only one way of a communication path as a working direction. When communication failure occurs, the path direction used in the normal operation is switched to the reverse direction (protection direction) so that the communication failure can be quickly responded. As shown in FIG. 10A, for example, in the normal operation of the ring network including four optical transmission apparatuses, i.e. a node 1 to a node 4, an optical signal is sent from the node 4 to a node 2 using a path passing through a node 3.
In this state, when communication failure occurs between the node 4 and the node 3 as shown in FIG. 10B, the node 3 sends information of the communication failure to the node 4 through the node 2 and the node 1. In response to the information of the failure occurrence, the node 4 sends an optical signal to the node 2 using a reverse path direction (protection direction) of the current path direction. Specifically, the optical signal from the node 4 reaches the node 3 through the node 1 and the node 2, and turns around at the node 3 to be sent to the node 2.
In the “1+1 APS” or the “BLSR”, an optical transmission apparatus performs switching control of the APS function by exchanging with a neighboring optical transmission apparatus APS bytes (K1/K2 bytes) stored in the overhead of an SDH or a SONET optical signal. For example, when an optical transmission apparatus at the receiving end detects a failure such as a signal failure (SF) or signal degradation (SD), the apparatus notifies information of the failure to a neighboring apparatus using APS bytes storing such information, and performs switching control.
The switching control is performed within 50 milliseconds as required by the GR253 standard.
An example of an architecture realizing the “1+1 APS” or the “BLSR” is a centralized CPU (central processing unit) architecture as shown in FIG. 11. FIG. 11 is a schematic of a centralized CPU architecture.
As shown in FIG. 11, the centralized CPU architecture has a redundant configuration including: a CPU section that controls monitoring an entire optical transmission apparatus; and line interface units (LIUs), i.e., a first LIU and an second LIU, each having an interface function for external lines corresponding to working and protection lines. A user of the optical transmission apparatus sets via the CPU section, for example, the first LIU to be an interface for the working line, and the second LIU to be an interface for the protection line.
Each of the first LIU and the second LIU includes hardware units. The hardware receives APS bytes over the working and the protection lines, and notifies information of SF and SD to the CPU section. The hardware also performs switching in response to a command from the CPU section. Each of the first LIU and the second LIU has a plurality of ports corresponding to the working and the protection lines.
In the centralized CPU architecture, firmware operating in a CPU of the CPU section collects information of the APS bytes from the first LIU and the second LIU, so as to control switching.
For example, when the hardware of the first LIU serving as an interface for the working line detects SF as a switching factor, the hardware notifies the occurrence of the SF to the firmware of the CPU section (see (1) shown in FIG. 11). The firmware of the CPU section then performs an APS determination process (switching determination process), based on the received SF information and the information of APS bytes from the second LIU (see (2) shown in FIG. 11), so as to control switching of the hardware in the first LIU and the second LIU (see (3) shown in FIG. 11). In this way, switching is performed as shown in FIG. 9B or 10B.
In the centralized CPU architecture, when a plurality of switching factors occur concurrently, the CPU section is congested with the APS determination process performed by the firmware, causing a problem that switching cannot be performed quickly for such a communication failure.
The problem is addressed with an architecture realizing a “1+1 APS” or a “BLSR”, such as a decentralized or distributed CPU architecture shown in FIG. 12. FIG. 12 is a schematic of a distributed CPU architecture.
As with the centralized CPU architecture, the distributed CPU architecture includes a CPU section, and a first LIU and a second LIU each having an interface function for external lines corresponding to the working and the protection lines, as shown in FIG. 12. Each of the first LIU and the second LIU includes a distributed CPU. Firmware operating in the CPU of one LIU collects information of APS bytes, and communicates it with firmware of the other LIU. Accordingly, information of both LIUs is shared to control switching.
As in the centralized CPU architecture, a user of the optical transmission apparatus sets via the CPU section, for example, the first LIU to be an interface for the working line and the second LIU to be an interface for the protection line. The first LIU receives such setting information via firmware (user I/F unit) in a CPU of the CPU section, and sets itself to be an interface for the working line. Similarly, the second LIU sets itself to be an interface for the protection line.
In the “1+1 APS”, as required by the GR253 standard, a CPU in an LIU set as an interface for the protection line (the second LIU in FIG. 12) is automatically set as a master CPU and dominantly controls switching of hardware. Further, a CPU in an LIU set as an interface for the working line (the first LIU in FIG. 12) is set as a slave CPU that relays a command from the master CPU to hardware of the LIU. In the “BLSR”, a user selectively sets a master CPU. For example, when the CPU in the second LIU is set as a master CPU, the CPU in the first LIU is set as a slave CPU that relays a command from the master CPU to the hardware of the first LIU.
In the distributed CPU architecture, for example, when the hardware of the first LIU serving as an interface for the working line detects SF as a switching factor, it notifies the occurrence of the SF to the firmware in the CPU of the first LIU (see (1) shown in FIG. 12). The firmware of the first LIU notifies the occurrence of the switching factor to the firmware in the CPU (master CPU) of the second LIU by firmware communication (see (2) shown in FIG. 12). The firmware of the second LIU performs the APS determination process (switching determination process), based on the switching factor (SF) received from the first LIU, the information of APS bytes from the second LIU, and the information indicating that the second LIU acts as the interface for the protection line (see (3) shown in FIG. 12).
The firmware of the second LIU provides a result of the APS determination process as a switching notification to the firmware of the first LIU by firmware communication (see (4) shown in FIG. 12). Based on the result determined by the firmware of the second LIU, the firmware of the first LIU and the firmware of the second LIU control switching of the hardware of their respective LIUs (see (5) shown in FIG. 12). As such, switching is controlled based on the determination made by the CPU of the second LIU serving as a master CPU, and thus performed, for example, as shown in FIG. 9B or 10B.
Japanese Examined Patent Application Publication No. H6-30002 discloses a programmable controller in which data is transferred by direct memory access (DMA) from a memory of a master CPU to a memory of a slave CPU, allowing the CPUs to share information Japanese Patent Application Laid-open No. H8-202672 discloses a distributed multiprocessing system that includes processor units (a single master unit and a plurality of slave units) each including a CPU and a memory, and that allows the CPUs to share information by transferring data from the master unit to the slave units via a VERSAmodule Eurocard (VME) bus.
In the conventional configuration, upon detection of a line failure in an LIU installed with a slave CPU, information of the failure needs to be notified to an LIU installed a master CPU, by firmware communication. Because it takes time to notify a large amount of information to the master CPU, switching cannot be performed quickly.
In the conventional configuration, upon occurrence of failure or removal of an LIU installed with a master CPU, a CPU in a neighboring LIU needs to perform the APS determination process as a master CPU. Because the CPU does not hold information of APS bytes having been collected by the master CPU before the occurrence of the failure or removal, switching cannot be performed properly.
In the related arts, upon recovery of an LIU installed with a CPU set as a master CPU, the CPU in the recovered LIU collects information of APS bytes from a CPU in a neighboring LIU. Because the CPU of the neighboring LIU does not hold information of APS bytes having been collected before the occurrence of the failure or removal, the collected information is incomplete. Thus, switching cannot be performed properly.
Such information of APS bytes is collected by firmware communication, thus taking time to collect the information and failing to perform quick switching. Particularly the “BLSR” having a ring network configuration communicates a larger amount of information compared with the “1+1 APS”, thus taking time to collect the information and failing to perform quick switching.